hsms-280x surface mount rf schottky barrier diodes data sheet description/applications these schottky diodes are specifically designed for both analog and digital applications. this series offers a wide range of specifica tions and package con figura tions to give the designer wide flexi bility. the hsms-280x series of diodes is optimized for high voltage applications. note that avagos manufacturing techniques assure that dice found in pairs and quads are taken from adjacent sites on the wafer, assuring the highest degree of match. package lead code identification, sot-23/sot-143 (top view) package lead code identification, sot-323 (top view) p ackage lead code identification, sot-363 (top view) features surface mount packages high breakdown voltage low fit (failure in time) rate* six-sigma quality level single, dual and quad versions tape and reel options available lead-free * for more information see the surface mount schottky reliability data sheet. common cathode #4 unconnected pair #5 common anode #3 series #2 single #0 12 3 12 34 bridge quad #8 12 34 12 3 12 3 12 3 common cathode quad m unconnected trio l bridge quad p common anode quad n ring quad r 123 654 high isolation unconnected pair k 123 654 123 654 123 654 123 654 123 654 common cathode f common anode e series c single b
2 absolute maximum ratings [1] t c = 25c symbol parameter unit sot-23/sot-143 sot-323/sot-363 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v same as v br same as v br t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25c, where t c is defined to be the temperature at the package pins where contact is made to the circuit board. notes: 1. package marking provides orientation and identification. 2. see electrical specifications for appropriate package marking. esd warning: handling precautions should be taken to avoid static discharge. pin connections and package marking, sot-363 gux 1 2 3 6 5 4 electrical specifications t a = 25c, single diode [3] part number hsms [4] package marking code lead code configuration minimum breakdown voltage v br (v) maximum forward voltage v f (mv) maximum forward voltage v f (v) @ i f (ma) maximum reverse leakage i r (na) @ v r (v) maximum capacitance c t (pf) typical dynamic resistance r d () [5] 2800 a0 0 single 70 410 1.0 @ 15 200 @ 50 2.0 35 2802 a2 2 series 2803 a3 3 common anode 2804 a4 4 common cathode 2805 a5 5 unconnected pair 2808 a8 8 bridge quad [4] 280b a0 b single 280c a2 c series 280e a3 e common anode 280f a4 f common cathode 280k ak k high isolation unconnected pair 280l al l unconnected trio 280m h m common cathode quad 280n n n common anode quad 280p ap p bridge quad 280r o r ring quad test conditions i r = 10 ma i f = 1 ma v f = 0 v f = 1 mhz i f = 5 ma notes: 1. dv f for diodes in pairs and quads in 15 mv maximum at 1 ma. 2. dc to for diodes in pairs and quads is 0.2 pf maximum. 3. effective carrier lifetime (t) for all these diodes is 100 ps maximum measured with krakauer method at 5 ma. 4. see section titled quad capacitance. 5. r d = r s + 5.2 at 25c and i f = 5 ma.
3 quad capacitance capacitance of schottky diode quads is measured using an hp4271 lcr meter. this instrument effectively isolates individual diode branches from the others, allowing accurate capacitance measurement of each branch or each diode. the conditions are: 20 mv r.m.s. voltage at 1 mhz. avago defines this measurement as cm, and it is equivalent to the capaci tance of the diode by itself. the equivalent diagonal and adja cent capacitances can then be calculated by the formulas given below. in a quad, the diagonal capaci tance is the capacitance between points a and b as shown in the figure below. the diagonal capacitance is calculated using the follow- ing formula c 1 x c 2 c 3 x c 4 c diagonal = _______ + _______ c 1 + c 2 c 3 + c 4 c 1 c 2 c 4 c 3 a b c the equivalent adjacent capacitance is the capacitance between points a and c in the figure below. this capaci- tance is calculated using the following formula 1 c adjacent = c 1 + ____________ 1 1 1 CC + CC + CC c 2 c 3 c 4 this information does not apply to cross-over quad diodes. spice parameters parameter units hsms-280x b v v75 c j0 pf 1.6 e g ev 0.69 i bv a e-5 i s a 3.00e-08 n 1.08 r s 30 p b v 0.65 p t 2 m 0.5 c j r j r s r j = 8.33 x 10 -5 nt i b + i s where i b = externally applied bias current in amps i s = saturation current (see table of spice parameters) t = temperature, k n = ideality factor (see table of spice parameters) note: to effectively model the packaged hsms-280x product, please refer to application note an1124. r s = series resistance (see table of spice parameters) c j = junction capacitance (see table of spice parameters) linear equivalent circuit, diode chip
4 typical performance, t c = 25c (unless otherwise noted), single diode 0 0.1 0.3 0.2 0.5 0.6 0.4 0.8 0.7 0.9 i f C forward current (ma) v f C forward voltage (v) figure 1. forward current vs. forward voltage at temperatures. 0.01 10 1 0.1 100 t a = +125c t a = +75c t a = +25c t a = C25c figure 2. reverse current vs. reverse voltage at temperatures. 0102030 50 40 i r C reverse current (na) v r C reverse voltage (v) 1 1000 100 10 100,000 10,000 t a = +125c t a = +75c t a = +25c figure 3. dynamic resistance vs. forward current. 0.1 1 100 r d C dynamic resistance () i f C forward current (ma) 10 1 10 1000 100 figure 4. total capacitance vs. reverse voltage. 0102030 50 40 c t C capacitance (pf) v r C reverse voltage (v) 0 1.5 1 0.5 2 v f - forward voltage (v) figure 5. typical v f match, pairs and quads. 30 10 1 0.3 30 10 1 0.3 i f - forward current (ma) v f - forward voltage difference (mv) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 i f (left scale) v f (right scale)
5 table 1. typical spice parameters parameter units hsms-280x hsms-281x hsms-282x b v v75 25 15 c j0 pf 1.6 1.1 0.7 e g ev 0.69 0.69 0.69 i bv a 1 e-5 1 e-5 1 e-4 i s a 3 e-8 4.8 e-9 2.2 e-8 n 1.08 1.08 1.08 r s 30 10 6 p b (v j ) v 0.65 0.65 0.65 p t (xti) 2 2 2 m 0.5 0.5 0.5 applications information introduction product selection avagos family of schottky products provides unique solutions to many design problems. the first step in choosing the right product is to select the diode type. all of the products in the hsms-280x family use the same diode chip, and the same is true of the hsms-281x and hsms-282x families. each family has a dif- ferent set of characteristics which can be compared most easily by consulting the spice parameters in table 1. a review of these data shows that the hsms-280x family has the highest breakdown voltage, but at the expense of a high value of series resistance (r s ). in applications which do not require high voltage the hsms-282x family, with a lower value of series resistance, will offer higher current carrying capacity and better performance. the hsms-281x family is a hybrid schottky (as is the hsms-280x), offering lower 1/f or flicker noise than the hsms-282x family. in general, the hsms-282x family should be the designers first choice, with the -280x family reserved for high voltage applications and the hsms-281x family for low flicker noise applications. assembly instructions sot-323 pcb footprint a recommended pcb pad layout for the miniature sot- 323 (sc-70) package is shown in figure 6 (dimensions are in inches). this layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the perfor- mance. 0 . 0 2 6 0 . 0 3 9 0 . 079 0 . 0 22 dime n sio n s i n i n c h es 0 . 0 2 6 0 . 079 0 . 018 0 . 0 3 9 dime n sio n s i n i n c h es figure 6. recommended pcb pad layout for avagos sc70 3l/sot-323 products. assembly instructions sot-363 pcb footprint a recommended pcb pad layout for the miniature sot- 363 (sc-70, 6 lead) package is shown in figure 7 (dimen- sions are in inches). this layout provides ample allowance for package placement by automated assembly equip- ment without adding parasitics that could impair the performance. figure 7. recommended pcb pad layout for avagos sc70 6l/sot-363 products.
6 figure 8. surface mount assembly profile. 25 t ime t empera t ure t p t l t p t l t 25 c t o pea k ramp - up t s t s min ramp - down prehea t cri t ica l z one t l t o t p t s ma x lead-free reflow profile recommendation (ipc/jedec j-std-020c) reflow parameter lead-free assembly average ramp-up rate (liquidus temperature (t s(max) to peak) 3c/ second max preheat temperature min (t s(min) ) 150c temperature max (t s(max) ) 200c time (min to max) (t s ) 60-180 seconds ts(max) to tl ramp-up rate 3c/second max time maintained above: temperature (t l ) 217c time (t l ) 60-150 seconds peak temperature (t p ) 260 +0/-5c time within 5 c of actual peak temperature (t p ) 20-40 seconds ramp-down rate 6c/second max time 25 c to peak temperature 8 minutes max note 1: all temperatures refer to topside of the package, measured on the package body surface smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot package, will reach solder reflow temperatures faster than those with a greater mass. avagos sot diodes have been qualified to the time- temperature profile shown in figure 8. this profile is representative of an ir reflow type of surface mount as- sembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. the reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. the rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. the maximum temperature in the reflow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assem- bly process for avago diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder.
7 package dimensions outline 23 (sot-23) outline sot-323 (sc-70 3 lead) part number ordering information part number no. of devices container hsms-280x-tr2g 10000 13 reel hsms-280x-tr1g 3000 7 reel hsms-280x-blkg 100 antistatic bag x = 0, 2, 3, 4, 5, 8, b, c, e, f, k, l, m, n, p, r e b e2 e 1 e1 c e xxx l d a a1 n o t es : xxx- pac k age mar k ing drawings are no t t o sca l e d i m ensions ( mm ) m in . 0.79 0.000 0.30 0.08 2.73 1 . 1 5 0.89 1 .78 0.45 2. 1 0 0.45 m ax . 1 .20 0. 1 00 0.54 0.20 3. 1 3 1 .50 1 .02 2.04 0.60 2.70 0.69 sy m bol a a1 b c d e1 e e 1 e2 e l e b e 1 e1 c e xxx l d a a1 n o t es : xxx- pac k age mar k ing drawings are no t t o sca l e d i m ensions ( mm ) m in . 0.80 0.00 0. 1 5 0.08 1 .80 1 . 1 0 1 .80 0.26 m ax . 1 .00 0. 1 0 0.40 0.25 2.25 1 .40 2.40 0.46 sy m bol a a1 b c d e1 e e 1 e l 1 .30 t ypica l 0.65 t ypica l
8 user feed direction cover tape carrier tape reel note: "ab" represents package marking code. "c" represents date code. end view 8 mm 4 mm top view abc abc abc abc note: "ab" represents package marking code. "c" represents date code. end view 8 mm 4 mm top view abc abc abc abc end view 8 mm 4 mm top view note: "ab" represents package marking code. "c" represents date code. abc abc abc abc device orientation for outline sot-143 for outlines sot-23, -323 for outline sot-363 outline 143 (sot-143) outline sot-363 (sc-70 6 lead) package dimensions (continued) e b e2 b1 e 1 e1 c e xxx l d a a1 n o t es : xxx- pac k age mar k ing drawings are no t t o sca l e d i m ensions ( mm ) m in . 0.79 0.0 1 3 0.36 0.76 0.086 2.80 1 .20 0.89 1 .78 0.45 2. 1 0 0.45 m ax . 1 .097 0. 1 0 0.54 0.92 0. 1 52 3.06 1 .40 1 .02 2.04 0.60 2.65 0.69 sy m bol a a1 b b1 c d e1 e e 1 e2 e l e he d e a1 b a a 2 l c d i m ensions ( mm ) m in . 1 . 1 5 1 .80 1 .80 0.80 0.80 0.00 0. 1 5 0.08 0. 1 0 m ax . 1 .35 2.25 2.40 1 . 1 0 1 .00 0. 1 0 0.30 0.25 0.46 sy m bol e d he a a 2 a1 e b c l 0.650 b c s
9 tape dimensions and product orientation for outline sot-23 for outline sot-143 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0.05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 - 0.10 0.229 0.013 0.315 + 0.012 - 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance between centerline w f e p 2 p 0 d p d 1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.19 0.10 2.80 0.10 1.31 0.10 4.00 0.10 1.00 + 0.25 0.126 0.004 0.110 0.004 0.052 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 - 0.10 0.254 0.013 0.315+ 0.012 - 0.004 0.0100 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance a 0 9 max 9 max t 1 b 0 k 0
tape dimensions and product orientation for outlines sot-323, -363 for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2010 avago technologies. all rights reserved. obsoletes 5989-4020en av02-0533en - april 14 , 2010 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.254 0.02 0.315 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance for sot-323 (sc70-3 lead) an 8 c max for sot-363 (sc70-6 lead) 10 c max angle width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape
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